As DRAMs increase in memory cell density, there is a continuous challenge to maintain a sufficiently high storage capacitance despite decreasing cell area. A principle way of increasing cell density is through cell structure techniques. Such techniques include three dimensional cell capacitors such as trenched or stacked capacitors.
With a conventional stacked capacitor, the capacitor is formed immediately above and electrically connected to the active device area of the associated MOS transistor of the memory cell. Typically, only the upper surface of the lower storage polysilicon node of the capacitor is utilized for capacitance. However, some attempts have been made to provide constructions to increase capacitance, whereby the backside of one capacitor terminal is used to store charge. Such is shown by way of example by T. Ema et al., "3-Dimensional Stacked Capacitor Cell For 16M And 64M DRAMS" IEDM Tech. Digest, pp. 592-595, 1988 and S. Inoue et al., "A Spread Stacked Capacitor (SSC) Cell For 64M BIT DRAMS", IEDM Tech Digest, pp. 31-34, 1989.
The article by Ema et al. discloses a construction for 16 and 64 megabit DRAMs. FIGS. 1 and 11 from this article illustrate a vertically rising capacitor construction having a plurality of horizontal fins, both sides of which are utilized for stored capacitance. The article to Inoue et al. utilizes spread of horizontal area for a three dimensional stacked capacitor construction. Both such process significantly add tedious processing steps over conventional techniques for creation of three dimensional stack cell capacitors, and require that tight tolerances be adhered to in contact alignment. Additionally, the processing disclosed by Inoue et al. creates difficulties in obtaining adequate coverage of applied material (such as the capacitor dielectric film) within the area beneath the horizontal fins.
It would be desirable to improve upon these and other processes in providing three dimensional stacked capacitors which maximize capacitance.